Pyramid Systems Development PSD



Electronics evolutions and revolutions - whether in component technology or in the products in which they are used - continue across the globe. While the world awaits the next electronic must-have marvel like the PC or the cell phone, the evolution and continual re-engineering of existing consumer, commercial and aerospace products is as fast-paced as ever. Electronics manufacturers continue their quest for products that provide greater functionality and consume less power, typically in packaging that gets smaller and smaller.

As a result of this continual evolution, new technologies and trends in the production of printed circuit boards are required, presenting new challenges for how PCBs are built and tested.

The current design trend continues toward a higher integration of ball grid arrays (BGAs), Gate arrays and FPGA's. New designs also include more programmable components and more serial busses. As constant as the evolution toward more advanced designs is the challenge of how the new designs will be tested in production. Almost universally, new designs will result in a higher complexity and less nets per board for testing. Another trend toward miniaturization has a dual benefit - components pack more capability into smaller packages, resulting in final products that are smaller than their previous-generation predecessors (again, PCs and cell phones are a good example).

Once again, however, what is a benefit to the end user is a detriment to those tasked with production testing. Miniaturization results in less available space for testing, with board sizes getting smaller and smaller and components mounted on both sides. These trends are responsible for an increasing number of multiple panels being used in today's electronic products.

In high volume products like automotive or consumer applications, the transition from single boards to multiple panels is especially high. By using multiple panel designs on today's better production machines, handling times are reduced and cycle times are faster. Unfortunately, a faster cycle time is counter-productive to the goal of performing comprehensive testing. Compounding the test time problem is the increased inclusion of steps such as memory test, component-programming, serial protocols and boundary scan on these more complex and more highly-integrated boards. As has always been the case, if the test time is not longer than the cycle time, test is not a problem; but if the test time is higher, testing is now a bottleneck that requires additional focus to remedy the situation.

The solutions to make test time shorter than cycle times can be broken down to two options:

• More testers and handlers i.e. more investment, more footprint

• Concurrent testing
Let's explore the feasibility of the two options. Adding more testers and handlers also seems to be an easy solution. Assuming that money and footprint are not issues (extremely unlikely), the issue then becomes how to integrate additional test systems into the production process. Complex mechanical solutions are necessary to integrate such solutions. Fixture costs and handler costs are additional cost to the complete multiplication of the tester hardware.

The second option, the incorporation of concurrent testing, is beneficial solution in many cases. Lambda gives the ability to test several boards simultaneously, i.e., in parallel using different test heads that are controlled through multiple controllers. The challenges of concurrent testing are mechanical as well as software issues that have to be resolved. The mechanical challenge is to minimize the size of the test head, so that the foot print of n test heads is much less that the foot print of n testers. Synchronizing the tests and collecting the test results in similar formats as the one tester, is part of the software challenges. However the mix of parallel and sequential operation is the major software challenge.

The solution was a reduction in size of the test head that allowed 4 test heads to be integrated in the space where originally one tester was fitted, i.e., the same foot print and the same tester size. One in-line handler can be used to handle the boards for the 4 test heads. Although the reduction in size affected the maximum number of test pins used such boards that are produced in multiple panel normally do not require high pin count.

Since the tester were not completely multiplied and one handler is used to handle the multiple panel board the costs for the 4 test heads including handler are 50-90% higher than the single tester. Compared to 400% cost increase if 4 testers were used and 3 additional handlers this is a major cost saving.

The concept reduce the test time by T/n where T the test time needed in case the panel will be tested sequentially i.e. one board at a time and n the number of test heads used. For example in case of the 4 test heads concept the test time will be reduced by 75%.

Lambda allows the user to perform all the tests that are necessary to ensure product quality without increasing the cycle time. The time needed for programming of flash memories will not be multiplied by the number of boards under test because testing and programming of the individual boards will be done simultaneously.

The next figure shows a block structure of the concurrent test concept:

The master controller loads the test program in each test head and initiates the test. The test head controller monitors the test and performs all the jumps, loops or test abortion if required. At the end of the test the test head controller feed back the test result to the master controller that create the datalog file and all other test end operations.

Some of the test resources could be external test such as VXI/IEEE instruments. Multiplication of these module could be either expensive or might need lots of space and thus foot print. Lambda concept represented here allows the mix between parallel (simultaneous) and sequential test. Thus such expensive modules could be shared during the test. The increase in test time depends on the duration of the single test. However time reduction of over 70 to 65% are typical.

The tester software generates the test program that will be loaded in each test head as well as the control program that will run on the master controller. Simple tools are provided to allow the user to easily determine where synchronizations points will be that will allow the jump from the parallel mode into the sequential mode to use some common resources.

The runtime software allows simple program debugging. One test program will be generated for all boards. By debugging this test program the whole test program for the complete panel is debugged. Simple case statements could count for board specific tests such as offset capacitances or board identification.

Failure handling, error reporting and program flow controls such as jump to test end if shorts were found or similar program flow controls are part of the runtime software.

The utilization of high level programming language and the powerful test commands facilitate the programming work.

While data collection of the various boards are handled by the test head controller at test end the master controller will collect the test data of different boards and generate one datalog file for the complete panel for paperless repair and the Quality management system.

Lambda is becoming a necessity to provide comprehensive testing without impacting production cycle times. Lambda includes real parallel test with small, affordable test heads; a powerful and flexible software environment; and, complete integration into an automatic board handler. The convergence of these elements demonstrates once again that a multi-dimensional test strategy can meet the evolving needs of technologies and methodologies in a high-volume electronics manufacturing environment, ensuring the delivery of top quality products to the market.

The concept of concurrent testing maximizes the depth of test and test coverage, the utilization of the tester hardware while minimizing the floor space impact and the costs of test hardware and handling systems.

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Over 110 major electronics manufacturers in 23 countries are depending on our testers and software tools to ensure quality aspects in their products from the design phase through production and test.

We are specialized in the development of both software and hardware for the international Computer Aided Engineering (CAE) market. We are dedicated to perfecting the manufacture and testing of Printed Circuit Boards (PCBs). Our automated software links Computer Aided Design (CAD) to the production, testing and repair of PCBs.

The software that we produce can be classified into two main categories: Design/Manufacturing and Testing/Quality Management. Our three major software products are C-LINK, CITE, and C-LINK QMan.